Second International Workshop on

New Frontiers in High-performance and Hardware-aware Computing

to be held in conjunction with the 17th IEEE International Symposium on High-Performance Computer Architecture

February 13, 2011
San Antonio, Texas, USA.

Workshop Organizers:
Rainer Buchty
Eberhard Karls University Tübingen, Germany
Jan-Philipp Weiß
Karlsruhe Institute of Technology, Germany

Steering Committee:
Vincent Heuveline
Karlsruhe Institute of Technology, Germany
Wolfgang Karl
Karlsruhe Institute of Technology, Germany

Program Committee:
David A. Bader
Georgia Tech, Atlanta, USA
Michael Bader
Univ. Stuttgart, Germany
Mladen Berekovic
Univ. Braunschweig, Germany
Alan Berenbaum
Martin Bogdan
Univ. Leipzig, Germany
Dominik Göddeke
TU Dortmund, Germany
Georg Hager
Univ. Erlangen, Germany
Vincent Heuveline
Karlsruhe Institute of Technology, Germany
Eric d'Hollander
Ghent University, Belgium
Michael Hübner
Karlsruhe Institute of Technology, Germany
Ben Juurlink
TU Berlin, Germany
Wolfgang Karl
Karlsruhe Institute of Technology, Germany
Rainer Keller
HLRS, Stuttgart, Germany
Hiroaki Kobayashi
Tohoku University, Japan
Harald Köstler
Univ. Erlangen, Germany
Dieter an Mey
RWTH Aachen, Germany
Andy Nisbet
Manchester Metropolitan University, UK
Christian Perez
INRIA, France
Franz-Josef Pfreundt
ITWM Kaiserslautern, Germany
Wolfgang Rosenstiel
Eberhard Karls University Tübingen, Germany
Olaf Schenk
Basel University, Switzerland
Martin Schulz
Masha Sosonkina
Ames Lab, USA
Thomas Steinke
Zuse-Institut Berlin, Germany
Josef Weidendorfer
TU Munich, Germany
Felix Wolf
GRS-SIM Aachen/Jülich, Germany

Rainer Buchty
Eberhard Karls University Tübingen, Germany

Jan-Philipp Weiß
Karlsruhe Institute of Technology, Germany

Workshop Flyer (PDF):
Workshop Program (PDF):

Workshop Website:

Conference Website:

HipHaC History (HHH):

Workshop theme: Heterogeneity and reconfigurability in computer systems are growing. Multi- and manycore-based systems are complemented by coprocessors, accelerators, and reconfigurable units providing huge computational power. However, applications of scientific interest (e.g., in high-performance computing and numerical simulation) are not yet ready to exploit the available high computing potential. Different programming models, non-adjusted interfaces, and bandwidth bottlenecks complicate holistic programming approaches for heterogeneous architectures. In modern microprocessors, hierarchical memory layouts and complex logics obscure predictability of memory transfers or performance estimations.

This workshop aims at combining new aspects of parallel, heterogeneous, and reconfigurable microprocessor technologies with concepts of high-performance computing and, particularly, numerical solution methods. Compute- and memory-intensive applications can only benefit from the full hardware potential if all features on all levels are taken into account in a holistic approach.

Workshop Program

Opening Session
  08:30 Welcome, Introduction & Overview

Session I: Processor Concepts and Emerging Architectures
  08:40 Convey HC-1 Hybrid Core Computer -- The Potential of FPGAs in Numerical Simulation
Werner Augustin, Jan-Philipp Weiß, and Vincent Heuveline
Karlsruhe Institute of Technology
  09:00 Optimized Replacement in the Configuration Layers of the Grid Alu Processor
Ralf Jahr1, Basher Shehan1, Sascha Uhrig2, and Theo Ungerer1
1Univ. Augsburg, 2TU Dortmund

Session II: Modelling of Data Traffic and Memory Behavior
  09:20 Traffic Prediction for NoCs using Fuzzy Logic
Gervin Thomas1, Ben Juurlink1, and Dietmar Tutsch2
1TU Berlin, 2Bergische Univ. Wuppertal
  09:40 Impact of Data Sharing on CMP design: A study based on Analytical Modeling
Anil Krishna, Ahmad Samih, and Yan Solihin
North Carolina State University

Coffee Break (10:00-10:30)

Session III: Algorithmic Aspects and Performance Evaluation
  10:30 Performance Engineering of an Orthogonal Matching Pursuit Algorithm for Sparse Representation of Signals on Different Architectures
Markus Stürmer1, Florian Rathgeber2, and Harald Köstler1
1Univ. Erlangen-Nürnberg, 2Imperial College London
  10:50 GPU Acceleration of the Assembly Process in Isogeometric Analysis
Nathan Collier1, Hyoseop Lee2, Aron Ahmadia1, Craig C. Douglas2, and Victor M. Calo1
1King Abdullah Univ. of Science and Technology Thuwal, 2Univ. of Wyoming
  11:10 GPU Accelerated Scientific Computing: Evaluation of the NVIDIA Fermi Architecture; Elementary Kernels and Linear Solvers
Hartwig Anzt, Tobias Hahn, Björn Rocker, and Vincent Heuveline
Karlsruhe Institute of Technology

Closing Session
  11:30 Future Directions in the Manycore Era
Open Discussion
  11:45 Wrap-up & Closing

The selected papers are published as printed workshop proceedings (ISBN 978-3-86644-626-7) through KIT Scientific Publishing

You can order your individual copy from here or download the proceedings for free

In case of any questions please contact the workshop organizers.